(a) Field of the Invention
The present invention relates to a semiconductor device having layered chips and, more particularly, to a semiconductor device having a plurality of semiconductor chips layered one on another.
(b) Description of the Related Art
Recent developments of digital-data electronic appliances in terms of smaller dimensions as well as higher performances require semiconductor packages to have smaller dimensions as well as a higher density. In the semiconductor packaging technology, a semiconductor device having a plurality of layered semiconductor chips now attracts larger attentions in view of the possibility of a higher density. This technology is generally used in digital-data electronic appliances, such as portable phone, digital camera and personal data assistant, which are required to have smaller weights as well as smaller dimensions and higher performances.
FIG. 8A shows a conventional semiconductor device having a multi-layered semiconductor chips in a top plan view thereof, whereas FIG. 8B shows the same semiconductor device in a sectional view taken along A-A in FIG. 8A. The semiconductor device 200 includes a base substrate 201, and a bottom semiconductor chip 2021 having a largest size, another semiconductor chip 2022 having a medium size, and a top semiconductor chip 2023 having a smallest size, which are layered on the base substrate 201 in this order.
Each semiconductor chip 202 has a peripheral area on which electrode pads 203 are disposed. The base substrate 201 and the semiconductor chips 202 are interconnected between electrode pads 203 thereof by using bonding wires 204. In the configuration of the semiconductor device 200, an underlying semiconductor chip 202 must have smaller dimensions compared to the overlying semiconductor chip 202.
In the semiconductor device 200 shown in FIGS. 8A and 8B, the electrode pads 203 should have a width of around 100 μm or above in order for achieving reliable connections between the bonding wires 204 and the electrode pads 203. In addition, the pitch of the electrode pads 203 should not be extremely small, and thus, the number of electrode pads 203 disposed in the semiconductor chip 202 is limited.
If, for example, the semiconductor chip 202 is implemented as a DRAM (dynamic random access memory) chip, the electrode pads 203 should be disposed for, in addition to the power source terminal (source terminal) and the ground terminal, a large number of signal terminals such as address signal, command signal, and data signal terminals. Thus, the number of electrode pads 203 assigned to the source terminal and ground terminal is limited.
A semiconductor device having multi-layered semiconductor chips having equivalent dimensions among them is described in Patent Publication JP-A-10-163411, for example. FIG. 9 shows the described semiconductor chip in a sectional view thereof. In this technique, after a plurality of semiconductor chips 301 having the same dimensions are layered one on another, a plurality of plugs (electrodes) 303 made of conductive resin are formed which penetrate the layered semiconductor chips 301 at the positions where electrode pads 302 are located. This technique allows reduction in the dimensions of the semiconductor chips because the bonding pads for the bonding wires need not be provided.
In the structure of the semiconductor device 300 shown in FIG. 9, although the number of electrode pads can be increased compared to the semiconductor device 200 shown in FIGS. 8A and 8B, the semiconductor device 300 may involve problems as detailed below, if the source electrodes and ground electrodes are disposed apart from the signal electrodes.
FIG. 10 shows, in a perspective view, a conceivable structure for a DRAM device implementing the semiconductor device 300 shown in FIG. 9, wherein a signal electrode is disposed apart from the source electrode and the ground electrode. Specifically, the semiconductor device 400 includes an IF (interface) chip 401 and four DRAM chips 402 (4020 to 4023) consecutively layered on the IF chip 401. The electric power supplied from an external power source to the IF chip 401 is supplied through an inter-chip power source electrode (source electrode) 403 and an inter-chip ground electrode 404 to an intra-chip source line 405 and an intra-chip ground line 406, respectively, of each of the DRAM chips 402. Each DRAM chip 402 has a plurality of drivers 407 in the peripheral area thereof, which operate on the electric power supplied through the intra-chip source line 405 and intra-chip ground line 406. The output signal of each driver 407 is fed through the inter-chip signal electrode 408 and the IF chip 401 toward an external circuit.
It is assumed here that a driver 407 disposed in the top DRAM chip 4023 now delivers an output signal that rises from a low level to a high level. A charge current flows in the direction of arrow 409 to charge an inter-chip signal electrode 408 connected to the output of the driver 407. More specifically, the charge current flows from the external high-potential power source line, through the IF chip 401, inter-chip source electrode 403, intra-chip source line 405, inter-chip signal electrode 408 and the IF chip 401 to return to the external low-potential power source line (ground line), whereby the charge current flows through a three-dimensional current path.
When the output of the driver 407 in the top DRAM chip 4023 changes from a low level to a high level, as described above, electromagnetic noise is generated outside the semiconductor device 400, depending on the loop area, magnitude and frequency components of the charge current. This type of semiconductor device 400 emits a relatively higher level of the electromagnetic noise due to the structure of the inter-chip electrodes. In addition, cross-talk is also generated between two signal inter-chip signal electrodes 408 extending parallel and adjacent to one another.